The invention relates to a field number doubling circuit for a television signal, comprising a memory circuit which can be written at the field frequency of the television signal to be doubled in field number and can be read at the double field frequency thereof, vertical synchronizing signals for a picture display section for displaying a television signal doubled in field number being derived by means of a controllable counter circuit from vertical synchronizing signals of the television signal to be doubled in field number for obtaining a vertical synchronizing signal pattern in which a vertical frequency component of the television signal to be doubled in field number is reduced. A field number doubling circuit of the type described above is known from European Patent Application No. 109,099, corresponding to U.S. Pat. No. 4,587,557. As is shown in FIG. 5 of this patent application, a first read operation of the memory circuit in this circuit is started at the end of a write operation and a second read operation is started at an instant which for a nominal television signal is halfway between the end of a write operation and the start of the next write operation. A field frequency component in the vertical synchronising pattern of the picture display section is reduced thereby so that a display with reduced flicker occurs.